 SU.HARDW.SCHEMES (2:5020/299)  SU.HARDW.SCHEMES 
 From : Alexej Vladimirov                   2:5100/22.1     Mon 23 Jan 95 12:59 
 Subj : .p奬 93C56                                                        


  "Microchip data book", 1994. P. 5-175...5-184

93c56 - 2K (256x8 or 128x16) CMOS Serial Electrically Erasable PROM.
Pin configuration:
      =====                      =====
 CS -|1 U 8|- Vcc           CS -|1===8|- Vcc
CLK -|2   7|- Test         CLK -|2   7|- Test
 DI -|3   6|- Org           DI -|3   6|- ORG
 DO -|4   5|- Vss           DO -|4   5|- Vss
      =====                      =====
    DIP 93C66                  SOIC 93C66

DC Characteristics:
                                 min     max             conditions
Vcc detector treshold, V         2.3     4.5
High level input voltage, V      2.0    Vcc+1
Low level input voltage, V      -0.3     0.8
High level output voltage, V     2.4                 Ioh= -400 uA
Low level output voltage, V              0.4         Iol= 2.1 mA
Input leakage current, uA                10          Vin= 0V to Vcc
Output leakage current, uA               10          Vout= 0V to Vcc
Internal capacitance, pF                  7          f= 2MHz
Operating current, mA                     4          f= 2MHz
Standby current, uA                      130         CS= 0V, Vcc= 5.5V x8 org
                                         100         CS= 0V, Vcc= 5.5V x16 org

AC Characteristics:
                                                         min   max   conditions
Endurance                                              100000        R/W cycles
Clock frequency, MHz                           Fclk             2
Clock high time, ns                            Tckh      500
Clock low time, ns                             Tckl      500
Chip select setup time, ns                     Tcss       50
Chip select hold time, ns                      Tcsh       0
Chip select low time, ns                       Tcsl      100
Data input setup time, ns                      Tdis      100
Data input hold time, ns                       Tdih      100
Data output delay time, ns                     Tpd              400   Cl=100 pF
Data output disable time (from CS=low), ns     Tcz              100   Cl=100 pF
Status valid time, ns                          Tsv              100   Cl=100 pF
Program cycle time (Auto Erase & Write), ms    Twc         1          x8 org
                                                           2          x16 org
Erase cycle time, ms                           Tec         15      ERAL & WRAL

Synchronous data timing:

                 Tckh             Tckl
          |______________| |               | __________________
CLK______/|               \|_______________|/|                 \___________
          |                                  |
     |Tdis| Tdih  |                          |
____ | __________ | _________________   _____________   ___________________
 /\ \ /  valid   \ /\ /\ /\ /\ /\ /\ \ /   valid     \ /\ /\ /\ /\ /\ /\ /\
DI/_/ \__________/ \/_\/_\/_\/_\/_\/_/ \_____________/ \/_\/_\/_\/_\/_\/_\/
          |                                  |
      |Tcss                                  |                   | Tcsl|
      |__________________________________________________________|     |____
CS___/    |                                  |                   |\___/
          |                                  |                   |
          |  Tpd   |                         | Tpd |             |Tcz|
__________________ | _____________________________ | _______________ |
                  \ /          valid              \ /    valid      \|_HIGH_
DO________________/ \_____________________________/ \_______________/



Instruction set (ORG=1 - x16 organization)

instruct start  opcode       address           number of  data out   CLK
          bit  OP1 OP2                          data in             cycles
  READ     1    1   0   X A6 A5 A4 A3 A2 A1 A0             D15-D0     27
  WRITE    1    0   1   X A6 A5 A4 A3 A2 A1 A0   D15-D0  (RDY/^BSY)   27
  ERASE    1    1   1   X A6 A5 A4 A3 A2 A1 A0           (RDY/^BSY)   11
  EWEN     1    0   0   1  1  X  X  X  X  X  X             High-Z     11
  EWDS     1    0   0   0  0  X  X  X  X  X  X             High-Z     11
  ERAL     1    0   0   1  0  X  X  X  X  X  X           (RDY/^BSY)   11
  WRAL     1    0   0   0  1  X  X  X  X  X  X   D15-D0  (RDY/^BSY)   27


Instruction set (ORG=0 - x8 organization)

instruct start  opcode       address              number of data out   CLK
          bit  OP1 OP2                            data in             cycles
  READ     1    1   0   X A7 A6 A5 A4 A3 A2 A1 A0            D7-D0      20
  WRITE    1    0   1   X A7 A6 A5 A4 A3 A2 A1 A0  D7-D0   (RDY/^BSY)   20
  ERASE    1    1   1   X A7 A6 A5 A4 A3 A2 A1 A0          (RDY/^BSY)   12
  EWEN     1    0   0   1  1  X  X  X  X  X  X  X            High-Z     12
  EWDS     1    0   0   0  0  X  X  X  X  X  X  X            High-Z     12
  ERAL     1    0   0   1  0  X  X  X  X  X  X  X          (RDY/^BSY)   12
  WRAL     1    0   0   0  1  X  X  X  X  X  X  X  D7-D0   (RDY/^BSY)   20

᫨  pᮢ ᠬ p奬 - ⬠ pls   
avlad@memec.apex.arcus.lv -  樠 p⠢⥫ p Microchip,
᪠饩 让 p祭 p⠫ p PIC  ᫥⥫ NVRAM.

--- GoldED/386 2.50.B0822+
 * Origin: * AV_Point - Riga, Latvia * (2:5100/22.1)

