 SU.HARDW.OTHER (2:5020/299)  SU.HARDW.OTHER 
 From : Alexej Vladimirov                   2:5100/73.1     Wed 11 Dec 96 15:53 
 Subj : 93ᕕ                                                                   


10 Dec 96, Sergey Lekanov writes to Everyone:

 SL> ᪠ p p   9306, 9346, 9356, 9366.

 p p:

=== Cut ===
From : Alexej Vladimirov           2:5100/22.1             24 Dec 93  00:52:42
To   : Leonid Avtushenko           2:5030/3                24 Dec 93  01:11:06
Subj : 93C06


  "Microchip data book", 1992. P. 1-97...1-102

93c06 - 256 byte (16x16) CMOS Serial Electrically Erasable PROM.
Pin configuration:
      =====
 CS -|1 U 8|- Vcc
CLK -|2   7|- Test
 DI -|3   6|- Test
 DO -|4   5|- Vss
      =====
  DIP, SO 93C06

DC Characteristics:
                                 min     max             conditions
Vcc detector treshold, V         2.8     4.5
High level input voltage, V      2.0    Vcc+1
Low level input voltage, V      -0.3     0.8
High level output voltage, V     2.4                    Ioh= -400 uA
Low level output voltage, V              0.4            Iol= 3.2 mA
Input leakage current, uA                10             Vin= 0V to Vcc (1)
Output leakage current, uA               10             Vout= 0V to Vcc (1)
Internal capacitance, pF                  7             f= 1MHz
Operating current, mA                     4             f= 1MHz
Standby current, uA                      100            CS= 0V, Vcc= 5.5V
Note (1): Internal resistor pull-up at Pin 6.

AC Characteristics:
                                                         min   max   conditions
Clock frequency, MHz                           Fclk             1
Clock high time, ns                            Tckh      500
Clock low time, ns                             Tckl      500
Chip select setup time, ns                     Tcss       50
Chip select hold time, ns                      Tcsh       0
Chip select low time, ns                       Tcsl      100
Data input setup time, ns                      Tdis      100
Data input hold time, ns                       Tdih      100
Data output delay time, ns                     Tpd              400   Cl=100 pF
Data output disable time (from CS=low), ns     Tcz              100   Cl=100 pF
Data output disable time (from last clock), ns Tddz             400   Cl=100 pF
Status valid time, ns                          Tsv              100   Cl=100 pF
Program cycle time (Auto Erase & Write), ms    Twc         2
                                                          15        ERAL & WRAL
Erase cycle time, ms                           Tec         1

Synchronous data timing:

                 Tckh             Tckl
          |______________| |               | __________________
CLK______/|               \|_______________|/|                 \___________
          |                                  |
     |Tdis| Tdih  |                          |
____ | __________ | _________________   _____________   ___________________
 /\ \ /  valid   \ /\ /\ /\ /\ /\ /\ \ /   valid     \ /\ /\ /\ /\ /\ /\ /\
DI/_/ \__________/ \/_\/_\/_\/_\/_\/_/ \_____________/ \/_\/_\/_\/_\/_\/_\/
          |                                  |
      |Tcss                                  |                   | Tcsl|
      |__________________________________________________________|     |____
CS___/    |                                  |                   |\___/
          |                                  |                   |
          |  Tpd   |                         | Tpd |             |Tcz|
__________________ | _____________________________ | _______________ |
                  \ /          valid              \ /    valid      \|_HIGH_
DO________________/ \_____________________________/ \_______________/



Instruction set:

instruction start   opcode       address       number of     data out   CLK
             bit   OP1 OP2                      data in                cycles
  READ        1     1   0    0  0 A3 A2 A1 A0                 D15-D0     25
  WRITE       1     0   1    0  0 A3 A2 A1 A0   D15-D0      (RDY/^BSY)   25
  ERASE       1     1   1    0  0 A3 A2 A1 A0               (RDY/^BSY)    9
  EWEN        1     0   0    1  1  X  X  X  X                 High-Z      9
  EWDS        1     0   0    0  0  X  X  X  X                 High-Z      9
  ERAL        1     0   0    1  0  X  X  X  X               (RDY/^BSY)    9
  WRAL        1     0   0    0  1  X  X  X  X   D15-D0      (RDY/^BSY)   25

Read mode:

 DI     1  1  0   0  0 A3 A2 A1 A0
 DO                                D15 D14 D13 D12 D11 ... D2 D1 D0

Write mode:

 DI     1  0  1   0  0 A3 A2 A1 A0 D15 D14 D13 D12 D11 ... D2 D1 D0
 DO                                                                   BSY RDY

Erase mode:

 DI     1  1  1   0  0 A3 A2 A1 A0
 DO                                BSY RDY

Erase/Write enable/disable (EWEN,EWDS) mode:

 DI     1  0  0  1/0 1/0  X  X  X  X

Erase all (ERAL) mode:

 DI     1  0  0  1  0  X  X  X  X  X
 DO                                  BSY RDY

Write all (WRAL) mode:
                                     D15          D1 D0
 DI     1  0  0  0  1  X  X  X  X  X  X  X  X  ... X  X
 DO                                                     BSY RDY

Pin Description:
Chip Select (CS)
A HIGH level selects the device. A LOW level deselects the device and forces it
into standby mode. However, a programming cycle which is already initiated
and/or in progress will be completed, regardless of the CS input signal. If CS
is brought LOW during the programming cycle, the device will go into standby
mode as soon as the programming cycle will be completed.
CS must be LOW for 100 ns minimum (Tcsl) between consecutive instructions. If
CS
is LOW, the internal control logic is held in a RESET status.

Serial clock (CLK)

The serial clock is used to sinhronize the communication between a muster
device
and the 93C06. Opcode, address, and data bits are clocked in on the positive
edge of CLK. Data bits are also clocked out on the positive edge of CLK.
CLK can be stopped anywhere in the transmission sequence (at HIGH or LOW level)
and can be continued anytime (with respect to clock HIGH time Tckh and clock
LOW
time Tckl). This gives the controlling master freedom in preparing opcode,
address and data.
CLK is a "Don't Care" if CS is LOW (device deselected). If CS is HIGH, but
START
condition has not been detected, any number of clock cycles can be received by
the device without changing its status (i.e waiting for START conditions).
CLK cycles are not requred during the self-timed WRITE (i.e auto ERASE/WRITE)
cycles.
After detection of a START condition, the specified number of clock cycles
(respectively LOW to HIGH transitions of CLK) must be provided. These clock
cycles are required to clock in all required opcode, address, and data bits
before an instruction is executed (see instruction set truth table). CLK and DI
then become "Don't care" inputs waiting for a new start condition to be
detected.
Note: CS must go LOW between consecutive instructions.

Data in (DI)

Data in is used to clock in Start bit,opcode, address and data sinhronously
with
the CLOCK input.

Data Out (DO)

Data Out is used in the READ mode to output data synhronously with the CLK
input
(Tpd after the positive edge of CLK).
This pin is also provides READY/^BUSY status information during ERASE and WRITE
cycles. READY/^BUSY status information is available on the DO pin if CS is
brought high after being low for minimum chip select low time (Tcsl) from the
failing edge of the CLK which clocked in the last DI bit (DO for WRITE, A0 for
ERASE) and an ERASE and WRITE operation has been initiated.
The status signal isn't available on DO, if CS is held LOW or HIGH during the
entire WRITE or ERASE cycle. In all other cases DO is in the HIGH-Z mode. If
status is checked after the WRITE/ERASE cycle, a pull-up resistor on DO is
required to read the READY signal.
DI and DO can be connected together to perform a 3-wire interface (CS,
CLK,DI/DO).
Care must be taken with the leading dummy zero which is outputted after a READ
command has been detected. Also, the controlling device must not drive the
DI/DO
bus during ERASE and WRITE cycles if the READY/^BUSY status information is
output by the 93C06.


 ⮬  p筨 ᠭ 24C01, 24C02, 24C04, 24C16, 59C11, 85C72,
85C82, 85C92, 93C06, 93C46, 93C56, 93C66, ER59256, 28C04, 28C16, 28C17, 28C64.

=== Cut ===


Alexej Vladimirov  avlad@mail.ormix.riga.lv  [Microchip technical support]

--- GoldED/2 2.50+
 * Origin: -=ORMIX=- http://www.ormix.riga.lv (2:5100/73.1)


