 SU.HARDW.CHAINIK (2:5100/22.1)  SU.HARDW.CHAINIK
From : Alexej Vladimirov                   2:5100/22.1     24 Dec 95  13:17:12
To   : Dima Golubev
 
  "Serial EEPROM Handbook", 1994. P. 2-159...2-166

85c82 - 2K byte (256x8) CMOS Serial Electrically Erasable PROM.
Pin configuration:
      =====
 A0 -|1 U 8|- Vcc
 A1 -|2   7|- NC
 A2 -|3   6|- SCL
Vss -|4   5|- SDA
      =====
  DIP, SO 85C82

DC Characteristics:
                                 min     max             conditions
Vcc detector treshold, V         2.8     4.5
SCL and SDA pins:
High level input voltage, V    Vccx0.7  Vcc+1
Low level input voltage, V      -0.3   Vccx0.3
Low level output voltage, V              0.4            Iol= 3.2 mA (SDA only)
A0,A1,A2 pins:
High level input voltage, V    Vcc-0.5  Vcc+0.5
Low level input voltage, V      -0.3     0.5
Input leakage current, uA                10             Vin= 0V to Vcc
Output leakage current, uA               10             Vout= 0V to Vcc
Internal capacitance, pF                  7             Vin/Vout= 0V
Operating current, mA                    3.5            Fclk= 100kHz, Vcc=5V
       read cycle, mA                    0.75           Vcc=5V
Standby current, uA                      100            SDA=SCL=Vcc=5V

AC Characteristics:
                                                         min   max   conditions
Clock frequency, kHz                           Fclk            100
Clock high time, ns                            Tckh      4000
Clock low time, ns                             Tckl      4700
SDA and SCL rise time, ns                      Tr             1000
SDA and SCL fail time, ns                      Tf              300
Start condition hold time, ns                  Thdsta    4000         (Note 1)
Start condition setup time, ns                 Tsusta    4700         (Note 2)
Data input hold time, ns                       Thddat       0
Data input setup time, ns                      Tsudat     250
Data output delay time, ns                     Tpd        300  3500   (Note 3)
STOP condition setup time, ns                  Tsu:sto   4700
Bus free time, ns                              Tbuf      4700         (Note 4)
Input filter time constant (SDA & SCL), ns     Ti               100
Program cycle time, ms                         Twc          0.4   1  byte mode
                                                            0.4*N N  page mode

Note 1: after this period the first clock pulse generated
Note 2: only relevant to repeated START condition
Note 3: as transmitter the device must provide the minimum delay time to bridge
the undefined region (minimum 300 ns) of the failing edge of SCL to avoid
unintended generation of START or STOP condition
Note 4: time the bus must be free before a new transmission can be start

Bus timing:

              | Tf|       | Thigh  |     Tlow    |            | Tr|
        ______|   |       | ______ |             | _____      |   |___________
      |/       \| |       |/      \|             |/     .     | |/
SCL__/|         |\|______/|        |\___________/|       .....|/|
      |  |      |                  |             |              |
Tsusta|<>|Thdsta|                  |Thddat|Tsudat|        Tsusto|<>| Tbuf  |
________ |      |       ___________|_____ | ___________......      | _____ |
        \|      |      /           |     \|/                       |/     \|
SDA IN   |\_____|____/_____________|_____/|\___________........___/|       |\_
                |                  |
                | Taa |            |Tdh|
_____________________ | ______________ | _____________________________________
\ /\ /\ /\ /\ /\ /\ /\|/              \|/
SDA OUT_\/_\/_\/_\/_\/|\______________/|\_____________________________________


Current address Read (SDA line):

 S                                     S
 T         A A A     D D D D D D D D   T
 A 1 0 1 0 2 1 0 1 0 7 6 5 4 3 2 1 0 1 O
 R                 A                   P
 T                 C
                   K

Random Read (SDA line):

 S                                     S                                     S
 T         A A A     W W W W W W W W   T         A A A     D D D D D D D D   T
 A 1 0 1 0 2 1 0 0 0 7 6 5 4 3 2 1 0 0 A 1 0 1 0 2 1 0 1 0 7 6 5 4 3 2 1 0 0 O
 R                 A                 A R                 A                   P
 T                 C                 C T                 C
                   K                 K                   K



Byte Write (SDA line):

 S                                                       S
 T         A A A     W W W W W W W W   D D D D D D D D   T
 A 1 0 1 0 2 1 0 0 0 7 6 5 4 3 2 1 0 0 7 6 5 4 3 2 1 0 0 O
 R                 A                 A                 A P
 T                 C                 C                 C
                   K                 K                 K

A0, A1, A2 - device address (pin 1,2,3). System cold have up to 8 85C82
on the bus.

W0...W7 - word address

D0...D7 - data
=== Cut ===


Alexej Vladimirov  avlad@mail.ormix.riga.lv  [Microchip technical support]

--- GoldED/2 2.50+
 * Origin: -=ORMIX=- http://www.ormix.riga.lv (2:5100/73.1)

