 299.COMP.SYS.INTEL (2:5020/299)  299.COMP.SYS.INTEL 
 From : rwallace@world.std.com              2:5020/299.100  Sun 30 Oct 94 03:19 
 Subj : DX-50 X2-X4?                                                            


  The Intel DX4-100 may be operated with 50 MHz external clock and
100 MHz internal clock (i.e. as a clock-doubled processor).

  The ratio between external and internal clock frequency of the DX4
is controlled through the "CLKMUL" input pin.  The voltage at this pin is
sampled during RESET, and the result is used to set the clock mode.  If
the pin is held "low", the internal clock frequency is set to twice the
external clock frequency.  This produces the "50/100" mode.  If the pin is
held "high", or is left floating, the internal clock is set to three times
the external clock frequency.  This produces the more common "33/100" mode.

  In addition to these modes, preliminary data sheets for the DX4
also described a "x2.5" mode -- e.g. 40 MHz external clock, 100 MHz
internal clock.  This mode was supposed to be available by connecting the
"CLKMUL" input pin to the "BREQ" output pin.  I have seen postings which
indicate that this mode is not supported in present DX4 chips.  However,
recently posted information on the P24T Pentium Overdrive processor describes
its operation in a "x2.5" mode: 33 MHz external / 83 MHz internal, so
it is possible that we may also see DX4 parts supporting the "x2.5" mode
in the future.

  With regard to operation of the DX4 in 50/100 mode, be aware that
Intel has two part designations in the DX4 (_not_ overdrive) family.  Parts
which carry an additional code ending in the numeric "877" have been tested
and qualified for both 33/100 and 50/100 operation.  Parts which carry an
additional code ending in "900" have been tested and qualified in 33/100
mode only.  A "900" part _may_ operate in 50/100 mode, but if operation in
this mode is a requirement, make sure to obtain the "877" part.

  I am hoping to see parts supporting the 40/100 mode at some time in
the future, but have no information indicating when, if ever, they might
be available.  The reason is that with current VLB motherboards, this mode
would make best overall use of the processor and peripherals.  Many newer
VLB cards support 40 MHz operation, showing a performance increase relative
33 MHz, but few will operate at 50 MHz.  Also, better VLB motherboards will
operate at 40 MHz with all cache and DRAM wait states set to minimum values.
At 50m MHz, wait states usually must be added, offsetting much of the
performance advantage of the higher external clock frequency.  In clock-
tripled mode, the DX4 can, in some types of code, become I/O bound -- the
processor can outrun the throughput capability of the 33 MHz interface to
external memory.  This problem would be reduced at 40 MHz external clock,
and should develop only rarely at 50 MHz with "typical" code, through which
a 486 averages approximately two (internal) clocks per instruction.  (See
486 Processor Hardware Reference Manual).

           Roger Wallace
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 * Origin: a kind of gate (2:5020/299.100)

 299.COMP.SYS.INTEL (2:5020/299)  299.COMP.SYS.INTEL 
 From : rwallace@world.std.com              2:5020/299.100  Sat 19 Nov 94 20:21 
 Subj : Re: ****** How do I verify/check CPU speed? *********                   


  The DX4 "Advance" Data Brief which I obtained from Intel's FAXBACK
service describes three clock modes for the DX4 processor, depending on the
connections to the CLKMUL pin:

  1) Internal clock = 3X external clock if CLKMUL is driven high or left
     floating.  (This appears to be the most commonly-used mode.)

  2) Internal clock = 2X external clock if CLKMUL is driven low or
           grounded

  3) Internal clock = 2.5X external clock if CLKMUL is connected to the
           BREQ output pin [pin Q15 for PGA package variants of the processor]

I have seen posts from what should be reliable sources indicating that the
present SX900 and SX877 variants of the DX4-100 do _not_ support the third
(2.5X) mode.  The ASUS VL/I-486SV2GX4 motherboard has jumper settings for the
2.5X mode, but selection of those settings results in 2X operation for the
SX900 DX4 processor which I have.  So, assuming the board correctly routes
signals to select the 2.5X mode, I have at least one data point indicating that
the posts re: 2.5X mode were correct.  In fairness, it should be noted that
advance information like that in the Data Brief is generally regarded as being
subject to change at the time of product release, after which product data
sheets are the official statement of specifications.

I for one would like to see the 2.5X mode available in DX4-100 processors.
This would permit 40/100 MHz operation with readily available hardware.
While 50/100 operation potentially has greater memory and I/O throughput,
few conventional motherboards can use 50 MHz local bus speed without adding
both external cache wait states and DRAM wait states which offset a good bit
of the available speed increase.  In contrast, quite a few good clone
boards, including the ASUS, will operate at 40 MHz with all wait states set
to minimum values.  Similarly, the selection of VLB video cards that will
operate at 50 MHz is limited, but many of the available cards operate very
well at 40 MHz in systems with only one or two VLB slots occupied.  There is
usually a noticeable improvement in video performance when local bus speed is
increased to 40 MHz from 33 MHz.

Further, since 486 processors average approximately two clocks per instruction
through "typical" code [ref: Intel 486 processor hardware reference manual --
some instructions one clock, a few much longer than 1 clock] , one can infer
that the DX4-100 in 33/100 mode will sometimes suffer from "memory bottleneck"
even when all access to external memory is in the form of 2-1-1-1 burst read
cycles from L2 cache.  Essentially no bottleneck would exist in 50/100 mode
_if_ L2 cache could be read in 2-1-1-1 bursts.  In 40/100 mode, there is still
some potential for the memory bottleneck, but with 2-1-1-1 burst reads from
L2 cache generally possible, the occurrences would be fewer.  The resulting
reduction in system performance would be smaller than that for 33/100 mode.

With the announcement of some details of the P24T, which is to run in
33.33/83.33 mode, Intel has shown a design which actually incorporates
a 32-bit processor running in 2.5X mode.  [Side note for Overclockers
Anonymous:  Keep your eyes open for the first post from an intrepid member
who fits a P24T with a Peltier cooler, and drops it into an upgradeable
486 motherboard, running at 40/100, with (say) 1 MB of 12-15 nsec L2
cache.]  I believe there was also mention (at the time of initial product
introduction) of a future variant of the DX4, intended for use in notebook
computers, that would operate in 2.5X (33/83) mode.

Are there any rumors or background rumblings about possible inclusion of the
2.5X mode in later steppings of the DX4-100 processor?

           Roger Wallace
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 * Origin: a kind of gate (2:5020/299.100)

