 SU.HARDW.PC.CPU (2:5020/299)  SU.HARDW.PC.CPU 
 From : Eugen Birkin                        2:5000/76.2     Mon 27 Jan 97 20:52 
 Subj : Cyrix optimization                                                      


Replying to a message of Vladimir Tinchurin to Eugen Birkin:

 EB>> ;***********************************************************
 EB>> ;*
 EB>> ;* Cyrix (IBM) 6x86 tuning program
 EB>> :* Based on "IBM 6x86 BIOS writer guide" (c) 1996, IBM
 EB>> ;* Written by Eugene Birkin (eu@seb.ru, 2:5000/76.2@fidonet)
 EB>> ;*
 EB>> ;***********************************************************

 VT>      ᫥ ⨬樨 ?

    1. Hᨬ  BIOS settings ⠢  WT_ALLOC

    WT_ALLOC
    Write Allocate (WT_ALLOC) allows L1 cache write misses to cause
    a cache line allocation. This feature improves the L1 cache hit
    rate resulting in higher performance especially for Windows
    applications.

    2. ⠢  ARR7 (᭮ RAM) ᫥騥 p:

    WR_GATHERING, WEAK_WRITE_ORDERING, CACHE_ENABLE

    Write Gathering (WG)

    Setting WG=1 enables write gathering for the corresponding
    address region. With WG enabled, multiple byte, word or dword
    writes to sequential addresses that would normally occur as
    individual write cycles are combined and issued as a single
    write cycle. WG improves bus utilization and should be used for
    memory regions that are not sensitive to the "gathering." WG can
    be enabled for both cacheable and non-cacheable regions.

    Weak Write Ordering (WWO)

    Setting WWO=1 enables weak write ordering for the corresponding
    address region. Weak Write Ordering allows the 6x86
    microprocessor to retire writes out of sequence to the internal
    cache only. External write cycles always occur in sequence
    (strongly ordered). WWO is only applicable to memory regions
    that have been cached and designated as write-back. WWO should
    never be enabled for memory mapped I/O.

    Region Cache Enable (RCE)

    Setting RCE=1 defines the corresponding address region as
    cacheable. RCE is applicable to ARR7 only. RCE in combination
    with ARR7, is intended to define the Main Memory Region. All
    memory outside ARR7 is non-cacheable when RCE is set. This is
    intended to define all unused memory space as non-cacheable. If
    KEN# is negated for an access within a region defined cacheable
    by RCE, the access is not cached.

    3.  ᥫ ;) p蠥 FAR COF's in BTB

    Branch Target Buffer (BTB)

    In the default state, the 6x86 microprocessor BTB stores target
    addresses for near change-of-flow instructions (COFs) only. To
    enhance the performance of the 6x86 microprocessor, the BTB
    should be configured to store target addresses for both near and
    far COFs. This feature is controlled through reserved
    configuration and test registers. 

    㭪 3 ᮡ ⥭  p뫪 쥬  ,祬
    pp p .     

 VT> Byes, Vladimir

 Eugen Birkin

--- FleetStreet 1.18+
 * Origin: C++ Sweet Home BBS, Novosibirsk (2:5000/76.2)


