 SU.HARDW.PC.CPU (2:5020/299)  SU.HARDW.PC.CPU 
 From : Aleksandr Konosevich                2:5004/9        Fri 26 Jan 96 14:57 
 Subj : Cx5x86/Cx6x86                                                           


᫥ p  p⥫쭮 ( !)   ᭮  !
쪮 ᥬ    p !  ᪮쪮   p p᫠ ! 8)

p    : 㢨 ⢮ ⪫  p  
"㣠"  Cx5x86 ( 316  380  100  120  ᮮ⢥⢥)
p宦  뢮 -   p    p 
䨣p樮 pp ᥣ pp,  p  "㣠"
  ᬮ   p.   易  ⨬
p :

a) pp  pp  ⥬ 㦤 ,  p 
 ,  ᪨  ᥬp,  p  p  ? 
 HACKER, , IMHO, ⢮ p  p檨 pᮢ p᫮
pﭮ,  ᮢp襭   ... :(

b) p 㤥 ppp_ᯫ⭮___,  㤥
 ᢮ pp   ᭮, ⮦__㤥_p 
_ᯫ⭮_!  㢨/㧭 p, p  ⮩ p樥
p - ᫮,    ! :E~  ⮡  ᭮ 뫮 -
,  ... Copyright (C) Cyrix Corporation. All rights reserved.
Portional copyright (C) Aleksandr K. Konosevich.   ᢮ p 
p   祣- p ... 8)

p,  ⢥  p  pp.

   - ᪮쪮 p     Cx5x86  Cx6x86 :

--- Cx5x86 ---

業  ⮨    - OIO.  ᨥ  ?
   p p ! H     ! 8)  (ᯮ,
p  -)  Official Invalid OpCode ! |))))))))))))
 0F FF. ,   ⠪ p᭮ 砭  FPU - The following
opcodes are reserved by Cyrix : D9D7, D9E2, D9E7, DDFC, DED8, DEDA, DEDC,
DEDD, DEDE, DFFC. If a reserved opcode executed, and unpredictable results
may occurs (exceptions are not generated).

--- Cx6x86 ---

H,    誨  OIO  FPU,    ,  p   :

Table 2-16. CCR5 Bit Definition

Bit   Name        Description

0     WT_ALLOC    Write-Through Allocate
                  If=1 : New cache lines allocated for read and write misses.
>                                                               ^^^^^^^^^^^^
                  If=0 : New cache lines allocated only for read misses.

4     LBR1        Local Bus Region 1
                  If=1 : LBA# pin is asserted for all accesses to the 640 Kbyte
                  to 1 Mbyte address region.

5     ARREN       Enable ARR Registers
                  If=1 : Enable all ARR registers.
                  If=0 : Disable the ARR registers. If SM3 is set, ARR3 is
                  enabled regardless of the setting of ARREN.

  p, _饣_w/b_cache  ᥬ⢥ 86  뢠 ? :)
뢠,  ⮫쪮   ⥫ ... |)))))))))))))

                          With best wishes, Aleksandr
--- 
 * Origin: ' ! 㫨 !  ⥫ !' (2:5004/9)


