 SU.HARDW.PC.CPU (2:5020/299)  SU.HARDW.PC.CPU 
 From : Lesha Bogdanow                      2:5095/9        Thu 25 Apr 96 18:48 
 Subj : 6x86                                                                    

          p All!

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=== register summary ===
Register Index Width MAPEN value

Configuration control registers

CCR0     C0    8     x
CCR1     C1    8     x
CCR2     C2    8     x
CCR3     C3    8     x
CCR4     E8    8     1
CCR5     E9    8     1

Address range registers

ARR0     C4-C6 24    x
ARR1     C7-C9 24    x
ARR2     CA-CC 24    x
ARR3     CD-CF 24    x
ARR4     D0-D2 24    1
ARR5     D3-D5 24    1
ARR6     D6-D8 24    1
ARR7     D9-DB 24    1

Region control registers

RCR0     DC    8     1
RCR1     DD    8     1
RCR2     DE    8     1
RCR3     DF    8     1
RCR4     E0    8     1
RCR5     E1    8     1
RCR6     E2    8     1
RCR7     E3    8     1

Device identification registers

DIR0     FE    8     x
DIR1     FF    8     x


======== Configuration control registers ===========

Bit Name     Description

CCR0

1   NC1      No cache 640Kb - 1Mb

CCR1

1   USE_SMI  Enable SMM and SMIACT# pins
2   SMAC     System Management memory access
4   NO_LOCK  Negate LOCK#
7   SM3      SMM Address Space Address Region 3

CCR2

2   LOCK_NW  Lock NW bit in CR0
3   SUSP_HLT Suspend on HLT
4   WPR1     Write protect region 1 (640K-1M)
7   USE_SUSP Use suspend mode (enable suspend pins)

CCR3

0   SMI_LOCK Lock SMM configuration bits: USE_SMI, SMAC, SM3,
             NMI_EN and ARR3 until RESET signal
1   NMI_EN   NMI enable
2   LINBRST  Use linear address sequence during burst cycles
4-7 MAPEN    MAP enable: configure access to configuration
             registers

CCR4

0-2 IORT     I/O recovery time: 0 = 1 clock, 1 = 2 clocks, ...,
             6 = 64 clock, 7 = No delay
4   DTE_EN   Enable directory table entry cache
7   CPUID    Enable CPUID instruction

CCR5

0   WT_ALLOC Write-through allocate: new cache lines are
             allocated both for read and write misses
4   LBR1     Local Bus region 1: LBA# pin is asserted for all
             accesses to the 640K-1M region
4   ARREN    Enable ARR registers


===== Address region registers and Region control registers ======

ARRs and RCRs are used to assign special attributes to 8 address regions.
ARRn format:

0-3 Size bits
4-23 Address bits (A31...A12)

Size bit values:
Size bits Size (ARR0..6) Size(ARR7)
0         disabled       disabled
1         4K             256K
2         8K             512K
            .               .
            .               .
            .               .
E         32M            2G
F         4G             4G

RCR bits define region attributes:

RCRx Bit Name Description
0-6  0   RCD  disables caching
7    0   RCE  enables caching
0-7  1   WWO  Weak write ordering
0-7  2   WL   Weak locking
0-7  3   WG   Write gathering
0-7  4   WT   Write-through
0-7  5   NLB  LBA# pin is not accerted

======== Device Identification registers (read-only) ==========
DIR0 - CPU device identification No

DIR1:
7-4 - CPU Step identification number
3-0 - CPU revision identification

=== Cut ===

          訬 ﬨ,
                        
--- p /2 2.50.A0715+
 * Origin: Boggy Place. Troitsk. (2:5095/9)


